1. Field of the Invention
The present invention relates to a driving circuit, a liquid crystal display apparatus and an electronic information device, and more particularly, the present invention relates to a driving circuit for driving a display panel, such as a liquid crystal display panel, which is configured to disperse peak current; a liquid crystal display apparatus equipped with such a driving circuit; and an electronic information device including such a liquid crystal display apparatus.
2. Description of the Related Art
Flat display apparatuses, such as a liquid crystal display apparatus, have conventionally included a display panel such as a liquid crystal display, a driver for driving the display panel, and a control circuit for controlling the driver.
In recent years, as these display apparatuses become larger, have higher definition and are driven faster, the output frequency of display signals (gradation voltage) to be output as display data to a display panel becomes higher and the number of display signals to be output increases. As a result, in a data driver for driving such a display panel, unnecessary radiation caused during data outputting has become problematic.
Hereinafter, a detailed description will be provided with an example of a conventional data driver for driving a display panel.
FIG. 14 is a block diagram describing a configuration of a conventional data driver.
A data driver 901 shown in FIG. 14 has n-numbered signal output terminals 911-1 to 911-n, and the data driver 901 is capable of outputting display signals for indicating display data (gradation data) of a p gradation from each of the output terminals to a data line of a display panel.
In summary, the data driver 901 includes, as signal input terminals to which signals are input from the outside, a clock input terminal 902, a plurality of gradation data input terminals 903, a control signal input terminal 904, and reference voltage terminals 905 to 909. The data driver 901 also includes n-numbered signal output terminals 911-1 to 911-n, from which signals are output to a liquid crystal display panel.
The data driver 901 includes, as internally provided circuits, a reference voltage correcting circuit 921, a pointer shift register section 923 for operating based on a clock signal CLK, a latch circuit section 924 for latching and sampling display data, a hold circuit section 925 for latching and holding latched-and-sampled display data, a D/A converter (Digital Analog Converter) section 926 for performing a D/A conversion on latched-and-held display data, and an output buffer section 927 for outputting display data subject to D/A conversion.
Herein, the pointer shift register section 923 includes n stages of shift registers 923-1 to 923-n. The latch circuit section 924 includes n latch circuits 924-1 to 924-n. The hold circuit section 925 includes n hold circuits 925-1 to 925-n. The D/A converter section 926 includes n D/A converter circuits 926-1 to 926-n. The output buffer section 927 includes n output buffers 927-1 to 927-n, each constituted of an operational amplifier.
Next, the operation of the apparatus described above will be described.
In the data driver 901 with such a configuration, an input of display data DATA, a data control signal LOAD, and a clock signal CLK from a control circuit (now shown) for controlling the driver 901 allows the pointer shift register section 923 to select one of latch circuits 924-1 to 924-n in accordance with the clock signal CLK input to the clock input terminal 902. In such a condition, an input of the gradation data DATA from the gradation data input terminal 903 causes a sampling value of the gradation data to be stored in the selected latch circuit in the latch circuit section 924.
In addition, latch circuit selection signals output from the pointer shift register section 923 cause a first stage latch circuit 924-1 to an nth stage latch circuit 924-n to be selected consecutively by the clock signal input from the clock input terminal 902. Therefore, an input of n clocks enables storage of the gradation data in all of the latch circuits 924-1 to 924-n. In addition, the gradation data stored in the latch circuits 924-1 to 924-n is transferred to corresponding n hold circuits 925-1 to 925-n by the control signal LOAD, to be digital input data of D/A converters 926-1 to 926-n. 
The D/A converters 926-1 to 926-n select and output one of p types of gradation voltages to be input, according to the digital input data above. P types of gradation voltages are generated by the reference voltage correcting circuit 921 based on reference voltages V0 to V4 input from respective reference voltage terminals 905 to 909.
Further, the output buffer section 927 performs an impedance conversion on the gradation voltages output from the D/A converters 926-1 to 926-n, and the gradation voltages are output to data lines of a liquid crystal display panel (not shown) as driving signals from each of the signal output terminals 911-1 to 911-n to the liquid crystal display panel.
In the conventional data driver 901 with such a configuration, since data transferring is performed from the hold circuits 925-1 to 925-n to the D/A converter circuits 926-1 to 926-n all together by the control signal LOAD as described above, the gradation voltages output from the D/A converter circuits 926-1 to 926-n are simultaneously changed. Thus, a large amount of current is generated instantaneously in the data driver 901. This current has an extremely large value due to the increase in the number of the signal output terminals 911-1 to 911-n and the increase in the driving performance by the output buffer section 927. Owing to this fact, not only is more current consumed by the data driver 901, but also unnecessary radiation caused by the current becomes problematic.
Accordingly, a method disclosed in Reference 1 has been proposed as a method for preventing peak current from increasing due to concentrated current.
FIG. 15 is a diagram describing a configuration of a data driver disclosed in Reference 1.
In a data driver 300 in FIG. 15, circuit blocks CB1 to CB4 correspond to the hold circuits, D/A converter circuits and output buffers in the data driver 901 shown in FIG. 14, and respective sets of the circuit blocks CB1 to CB4 are grouped by a plurality of groups CG1 to CGm. In summary, the circuit blocks CB1 to CB4 in each group correspond to respective data lines of a liquid crystal display panel, and they output display data to corresponding data lines.
Further, in the data driver 300, the control signal LOAD input via an input protection circuit E (30) is directly input into a first circuit group CG1. The control signal LOAD from the input protection circuit E (30) is input into a second circuit group CG2 via a first delay circuit 31a1. The control signal LOAD is input into a third circuit group CG3 via the first delay circuit 31a1 and a second delay circuit 31a2. In summary, the control signal LOAD is input into an m circuit group CGm via a first to m−1 delay circuits 31a1 to 31am-1.
Thus, in a liquid crystal display apparatus equipped with such a data driver, since there is a delay circuit D provided in between circuit groups CG, display output signals (gradation voltages) are output from respective circuit groups CG with each display output signal shifted by a delay period of time of each delay circuit D.
Owing to this configuration, display output signals are dispersed for respective circuit groups CG to be output. Therefore, peak current flowing through a power source line is dispersed even in a case where the number of signals is increased due to higher definition and a wider screen, and unnecessary radiation can also be reduced.
Reference 2 discloses subject matter which causes timing for taking gradation data into a hold circuit to be different between data drivers.
Reference 1: Japanese Laid-Open Publication No. 8-22267
Reference 2: Japanese Laid-Open Publication No. 2008-262132